Differential ADC (ADC1-ADC2)

Based on the topic on simultaneous conversion from ADC1 and ADC2 by jeremy777:
I’ve been thinking on using simultaneous ADC conversion from ADC1 and ADC2 to form a differential measurement – hoping to cancel the common mode noise (which is huge on MapleMini clones and BluePills). Perhaps the above code could be modified (or there is a library already) to work that way..
For example one shot measurement from ADC1 & ADC2 simultaneously and then do ADC1 – ADC2..
Something like this – ie. (maybe a core enhancement?)
int32_t readAnalog(PIN_U1, PIN_U2);

[Pito – Sat Sep 16, 2017 10:25 am] –
With simultaneous ADC conversion (the ADC1 samples in the exactly same time as the ADC2 does) the common noise voltage cancels (because we do u1 – u2).

… theoretically. But it did not work for me, I tried that a half a year ago, still got sporadically some differential noise.
Maybe due to unequal noise on GND or Vcc between ADC1 and 2.

How was the difference noise?

I wonder how “white/pink” the noise is. Given that most of it is likely to originate from the digital domain I suspect it pretty non-linear, and it may be possible to suppress it to some degree if we know what sort of spectrum it has.

I’ve spent a night reading posts (various forums) on STM32F1/2/4 ADCs problems.

There are 2 groups of people up there:
A. they say the STM32 silicon re ADC is sub-optimal, and the worse among others
B. they say the STM32 silicon is ok, but the PCB layouts used are mostly a crap (including commercial dev boards like discovery/nucleo etc).

A guy with a serious project – UPDATE the link https://community.st.com/thread/19850 and the pictures https://electronics.stackexchange.com/q … dc-noise-2 – elaborated pcbs (2 layers) with all the tricks with no success. The people involved into the discussion indicated both A and B positions. Then he finally accepted the B position and draw a 4 layer one (with separate gnds for analog and digital, dgnds and agnds connected together in a single point – at the agnd pin, no crossing of digital and analog tracks, etc). And he concluded at the end “the noise is gone” (unfortunately without any numbers, so take it or leave it..).

I tend currently to be in the group B, therefore my current naive understanding is it could be the ADC silicon works as advertised, therefore the differential scheme could work.

The noise coming from the ADC on our boards is not white/pink but it is a “digital” noise coming from poor grounding and pcb layout.
Noise suppression via averaging/digital filtering etc. is a workaround only..

Recall that the official Maple mini had separate analog and digital ground planes.
Baite (&others) went cloning with a dual-sided board … hence the increased analog noise.

Ray

oh well, i actually messed with this:
https://www.sparkfun.com/products/12650
and of course there are cheaper ‘knock offs’ from here:
https://www.ebay.com/sch/i.html?_from=R … 32&_sop=15
(think the ‘cheap’ ones may not be as safe it’s good to measure the resistances of the smd resistors and measure voltages, currents esp the probes)
that design supposedly does ‘right leg drive’ with an intent of removing common mode noise, i’d guess part of that may be that 50/60 hz hum
https://en.wikipedia.org/wiki/Driven_right_leg_circuit
but simply sitting near an ac source e.g. a switch mode usb charger, pc, etc is adequate to induce visible 50/60 hz noise mixing up with ECG signals (1mv average) the sparkfun’s breakout actually use the ad8232 for a low pass filter set at 40 hz cutoff, nevertheless hum is visible.
then i simply have do a software FIR filter to remove the rest of that hum.

my thoughts are that different resistances from the lead wires is sufficient to cause differences that they couldn’t be simply removed as ‘common mode noise’

an oh btw that sparkfun ad8232 breakout is pretty good as an analog front end for ecg paired with MM/BP
http://www.analog.com/en/products/appli … d8232.html
it removes a dc bias common in ecg meaaurements, removes baseline drift to an extent and centers the ecg around 1.5v out of 3v, amplifies that 1100 times based on sparkfun’s breakout and analog’s sample design,
then use an op amp in there to do an analog 40 hz cutoff low pass filter
that output can be simply plotted on an ili9341 with hardly any additional processing

that result is somewhat like this
https://github.com/sylvainf/stm32-ecg
but interfacing is a lot simplified with the ad8232 breakout, it is simply analogread and just plot that
however, i noted various artefacts which seem to be caused by the ad8232 itself, sometimes there are periodic spikes which i’m not too certain if it is introduced by the ad8232 or true ecg signals

just 2 c

thinking through this it would seem this differential adc could help remove some of that common mode noise, i could feed that ad8232 output into 2 ADCs and perhaps it may remove some of that artefact spikes

I run an ADS1110 (not in differential mode, -Vin at GND) on the same breadboard as the BPill + all the other stuff.
When I connect +Vin to a resistor divider 3k6/3k6 (divider from Vcc to GND, not blocked) to get 1.65V as the ADS1110 is max 2.048V, with 12cm long wire, and -Vin to GND (12cm wire and gnd) the ADS shows +/-1 reading (on 15bit resolution). The BPill’s 12bit ADC reads +/-30.
Yes, I know the ADS is fully different ADC (16bit, sigma-delta, 15meas/sec – sloow) but..

on this topic about noise, in part as i use low pass filtering, i’ve inherently ‘escaped’ some of the noise issues.
ecg signals are in the low orders of 5 hz – 40 hz (accordingly the range do extend upwards to say 50hz or somewhat more but of low amplitude), nevertheless low pass filtering set at 40 hz cut off removed some of the ecg signals and the ecg is less accurate.
however, as my aim is to capture between 5hz – 60hz range, i sampled at 150 sampl per secs and digitally low pass (FIR) filtered that with a 40 hz cutoff, my guess is that the low sampling rates and low pass filter removed quite a fraction of common mode or differential high frequency noises

but if you have to sample in the mhz (msps) ranges i’d think it would be difficult to remove noise this way and other means such as differential filtering or differential adc would likely matter significantly

[mrburnette – Sun Sep 17, 2017 10:02 pm] –
Recall that the official Maple mini had separate analog and digital ground planes.
Baite (&others) went cloning with a dual-sided board … hence the increased analog noise.

Ray

And the original had 4 layers vs 2 in the clones too.

I’m not sure if @pito’s original schematic is going to yield useful results.

Aren’t both ADC inputs going to suffer the same amount of common mode noise at the same time ?

I see that the 2 inputs have a resistor between them, but the value has not been specified, and even if there was a high value resistor, I’m don’t understand how that would help, it would just form a voltage divider with the input impedance on the ADC2

I can see if ADC2 is supplied with a clean reference voltage, that any changes in value have to be associated with supply noise, and this DeltaV from the actual reference voltage value, could be used to to remove noise from ADC1

But this presumes that supply noise has an equal numerical value on low input voltages e.g 0.3V as on high input voltages e.g. 3.0V

On a vaguely related topic. I’ve been experimenting with a HB100 doppler radar module, which has a very small signal output, of just a few mV, hence a multi stage opamp amplifier is used to increase the voltage output range to 0 – 3.3V

However, when I supply the HB100 and amplifier from the 3.3V pin on the BluePill, the amount of supply noise to the HB100 + amp, causes major problems and makes it unusable.

My current plan is to rebuild using an opamp with better common mode rejection, but also to supply from the 5V pin on the BP, and use a separate regulator for the 3.3V rail needed by the HB100, in the hope that gets around the supply noise problem

My experience is that the only way you get reasonable ADC values (having low noise +/-1 bit (!!), non-differential input) is to feed the BP from a battery (~3.6V).
Then I used to send the sampled values over SPI to another BP, having only GND and the SPI lines common for both BPs.
Important is to send the sampled values between sample periods:
– ADC (simultaneous dual) sample
– send data
– ADC (simultaneous dual) sample
– send data
and so on, so that no digital noise (SPI toggling) will affect the sampling.

I’m not sure if @pito’s original schematic is going to yield useful results.
The schematics above is not a “schematics”, it is rather a picture to depict the diff. Imagine all the wires there are complex elements (RLC)

The ADC1 and ADC2 have got the same VCC and VGND (an assumption which may not be valid in very detail), so the jumps on VCC and VGND rails (outside the chip) are for both ADCs the same (ok, we may start to discuss how the ADCs are connected to Vcc and Vgnd on the silicon..) – thus the differential mode will cancel the noise jumps.
I would be happy to try it on various boards, when a piece of code for simultaneous sampling of ADC1 and ADC2 is handy somewhere (here it must be really the “simultaneous mode”, a delay by a single clock would be a showstopper of such an exercise).

I would try supplying ADC2 with a stable reference voltage, e.g. even if this is just vcc via a resistor divider with a smoothing cap.

Then if you compare the last reading in ADC2 with the current reading, any difference should be he supply noise.