So when I tried to look at the STM32 at SPI DIV 2 it could not see the data at all
Looking on AliExpress there seem to be 100Mhz 16 channel analyzers which are compatible with the Saleae software (via some sort of 3rd party support)
e.g.
https://www.aliexpress.com/item/USB-Log … 90865.html
These are over 3 times more expensive, but thats not a surprise if they can actually sample at 100Mhz (though this may not be true)
Anyway, I wondered if anyone had one of these and could comment on whether it actually works
https://sigrok.org/wiki/PulseView
So far as I recall you can squeeze 24 MHz out of it if you limit yourself to <8 channels, or 12 MHz for more than 8. Of course that would be 24 mega samples per second, so you can only observe signals up to half that rate.
More info about these here -> http://www.jwandrews.co.uk/2011/12/sale … ogramming/
.. and here -> https://sigrok.org/wiki/Lcsoft_Mini_Board
I haven’t seen the model you linked to Roger, but I suspect it may be up to the job of grabbing data at 100 MHz. I await your results with interest. ![]()
To quote their website… “The Open Workbench Logic Sniffer is an open source logic analyzer with a USB interface. The hardware is designed for the SUMP open source logic analyzer client and toolchain. This project is a collaboration between the Gadget Factory and Dangerous Prototypes.“
I’ve heard good things about this little gadget, but I haven’t the need to spring the $$$ for it at the moment. As Pito stated, it can do 200 MS/s so will observe 36MHz or even 72MHz with ease.
You wont get much sample time though, unless you can think of some smart way to dump the data as fast as it arrives.
I also read an article (on HAD I think) about using a 74 series high speed buffer and reading straight in to a DIMM module at hundreds of MHz, then dumping it back out more slowly to the PC. A lot of work though, so if you don’t need the speed, or the head scratching, an off the shelf solution sounds more sensible.
You cannot run an LA on an mcu easily, as you need to trigger based on some rules. Evaluation of the rules for a trigger must be done in hw, also the triggering itself. A triggering via polling a pin or via an interrupt is a nogo when talking 200MHz or 100MHz sampling, of course.
I would not spend a single $ for an LA less capable than the OBLSniffer..
https://sigrok.org/wiki/Noname_XL-LOGIC16-100M
and here
https://sigrok.org/wiki/Mcupro_Logic16_clone
Sadly I cannot find “real” reviews for it.
OLS java software is also excellent.
this sounds somewhat like feedback for AliExpress, but is truly meant.
Stephen
Input buffer + Spartan3 + micro-controller for data download – the same as the OLS – that may work at 100MHz, sure.
PS: the OLS samples @100/200MHz into the fpga’s memory till the mem is full, then the memory is read by the pic18 mcu and data are sent to PC via usb (emulating 921k serial).
Not sure how the Aliexpress one works – see the note:
Q: it really can reach 100M samples.
A: Support 100M sampling mode. Supports up to 100M under Mode 3-way, if your computer is USB 2.0 support is not good for the high-speed mode may support less than a 3-way. This is not our product’s personality, but all SALEAE16 in common! Our products have passed before shipping 3-way test 100MHZ mode.
What does it mean Mode 3-way??
.. 2, using the computer’s memory as the acquisition memory, so you can to traditional logic analyzer memory depth can not be compared easily reach G-level storage depth.
..
4, can be flexibly set the sampling rate and the number of acquisition channels, 3-way acquisition time to achieve the highest sampling rate of 100M, 6 times to achieve 50M sampling rate, sampling rate to achieve the highest 32MHZ 9 Road, 16 Road, when the time to achieve the highest sampling rate of 16M.
It seems it supports direct data streaming into PC memory (OLS cannot do that) which is good when you need to analyze slower protocols with longer acquisition time.
Not sure it can do 100MHz directly into PC memory – maybe in “3Mode way” – what does it mean??
You have to read some reviews before you pull the trigger ![]()
I think the analyser i bought a few weeks ago has equivalent hardware to the board that Andy posted, except perhaps the eeprom which holds the USB ID is set so that the analyser is detected by the Saleae analyser software.
I will try that other software to see if it works with that as well.
It cost $9 and came with a small usb cable and some “dupont” wires, and its in a small box, which is why its a bit more expensive than the bare bones board that Andy posted.
I already have a 100MHz Rigol scope with 16 channel logic analyser, but the screen is quite small, and also it does not have any tools to analyse the data.
The PC software is much more user friendly and can show the actual values of the SPI data bytes etc.
But the analyser is too slow for me to figure out why the GD32 wont communicate with the ILI9341.
( well I suppose I could slow the whole thing down by changing the SPI DIV setting, but if its a timing issue at higher speeds I would not be able to debug it)
If the 100MHz analyser is a FPGA based on an open source design, it sounds more promising, especially if the FPGA could be reprogrammed for other uses as well.
Thanks again
Roger
I guess I should plug it into a different USB port on the PC and see if it performs any better.
I don’t think these 100M samples per second analysers are going to to be able to sustain that speed and transfer over USB to a PC.
I guess I should plug it into a different USB port on the PC and see if it performs any better.
I don’t think these 100M samples per second analysers are going to to be able to sustain that speed and transfer over USB to a PC.
Thats the way I would expect it to operate.
Does your analyser board work like this. Mine gives the impression that its sampling straight into the PC.
BTW. I have not had chance to look at the Open Source analyser software yet
as Ive been bogged down trying to get a small OLED screen working
The OLED is only 64×32 pixels, but most of the code I have found is for a minimum of 128×64
Thats the way I would expect it to operate.
Does your analyser board work like this. Mine gives the impression that its sampling straight into the PC.
BTW. I have not had chance to look at the Open Source analyser software yet
as Ive been bogged down trying to get a small OLED screen working
The OLED is only 64×32 pixels, but most of the code I have found is for a minimum of 128×64
OK. I think that my current analyser is basically the same as yours. Mine seems limited to 16M sampler per second, and doesnt seem to make much difference if I cut down the number of channels.
It probably always sends all 8 channels and its just the PC software that is only displaying 2 of them
A FPGA based analyser for under $50 is tempting, but I’ll need to read the specs, as RAM size (and speed) will be important
If the ones on AliExpress are based on an Open Source device; I’d rather go down that route.
The cheap analyser I have at the moment seems to be be based on an old Saleae logic 8, but uses a cypress MCU rather than fpga so is much lower performance.
Mine is compatible with the Saleae software, but I am not entirely sure how that works. Initially thought the cypress MCU must be flashed with a clone of the Saleae cypress firmware, but I also read that if you reprogram the eeprom that is on the board, to change the USB VID / PID that are stored in this external eeprom, that you can get the device to mimic a completely different analyser, without uploading any firmware to it
So the only way this seems possible is that the Saleae PC software is perhaps uploading firmware to the cypress MCU
Or the cypress MCU is not a MCU but some sort of generic analyser chip, which you just send config info via USB.
(I’d need to do more research to understand how it can be different devices without reflashing)
I was intending to use one of the open source logic analyzer software clients e.g. http://www.sump.org/projects/analyzer/client/
(As listed previously in this thread)
http://www.ebay.com/itm/USB-Logic-Analy … Swv0tVPjsy
The Q is what kind of back-end software it supports.
PS: 400MHz 4bit sampling is nice to have – ie. measuring 120MHz SPI on Teensy 3.6
![]()
More expensive than the 100M one i found on AliExpress, but much faster
It actually appears to be a real product from these guys
I also found this on the eevblog forum http://www.eevblog.com/forum/testgear/d … -400-mhz)/
I think a lot of complains come from people with less understanding what they do or what they should expect.
For $77 it is a great stuff, I must admit. You can hardly get a plain devboard with a spartan6 for that money.. ![]()
I purchased the OLS ~6y back (the demon fpga core was in early development at that time, no 200MHz sampling rate).
99.7% time I’ve been using it with max 2-3 signals and gnd connected. Usually SPI, sampling rates 100/200MHz, or when I mess with cpld/memories. I never ever used more than 5 wires ![]()
At the time I purchased the OLS I contributed a lot at the OLS forum – especially discussing/simulating/analyzing the probe inputs of the OLS, which are primitive – a piece of wire connected to the input buffer, no impedance matching, no ESD protection, no pullups, nothing. I even compared (w/ spice simulations) original HP LA probe designs with the OLS (various wire length, matching, etc). I designed a matched input with high-speed comparators and settable input level trigger level (got the chips but never soldered the stuff together). Finally we concluded it has no sense to mess a lot with it as it basically works with short wires as-is.
The most issue people “claim”:
1. when my sampling rate is 100MHz and I observe 40MHz clock, the signal I see is not symmetrical and its highs/lows varies. A: that is ok, think about sampling theory.
2. when I measure 33MHz clock at 200MHz sampling it shows 31-35Mhz frequency.. A: that is ok, mind your resolution is 5ns.
3. when using 50cm long flying probe leads and my sample rate is 200MHz I see small 5-10ns long pulses after the signal edges there and there. A: that is ok – that is the ringing of the flying probe, use 10cm max length, do match the probe and signal source ![]()
The above dreamlabs system is designed well for the money, the additional huge sdram memory is great, somebody has implemented RLE recently, with such memory you can sample SPI minutes long
.
I doubt, however, you can sample more than 100MSamples/sec into the external sdram
The internal maybe 64kBytes large fpga memory could work with 200-400Mhz, I would say.. That is enough for most measurements.
The OLS got 24kB of ram (fpga’s internal) and with RLE it is enough for 99.5% use cases
You are usually measuring a few SPI/I2C/rd/wr events/packets, so I would guess 8kB ram would be ok for all kinds of measurements I ever did ![]()
Except the HW the most important part is the client, of course. OLS started with sump-something and Thanks “jawi” who created the new OLS backend (btw, it took maybe 2y to get it well working) OLS has now a backend which works nice. You can zoom in/out, measure H/L periods, frequencies, markers with timings and diffs, a dozen of various decoders, etc. The dreamLabs provide updates – see the forum, so there is a chance their backend will work fine in the future..
PS: I’ve spent another hour browsing the old almost dead OLS forum – there are some “news” – 2y old one – Magnus has implemented “edge triggerring” what is cool, but I’m still not sure whether the OLS jawi client supports the “fpga advanced triggering” fully. Moreover, Magnus http://saanlima.com/forum/viewtopic.php … t=20#p1563 ported OLS to Pipistrello (basically the same setup as the above dreamlabs stuff – larger spartan and an external dram).
I agree, they are good value for money, but I am not sure whether I wanted to spend that much, or need that much bandwidth.
The smaller cheaper 100M FPGA analysers are probably more in my price range, as I dont have a project that really needs any of them ![]()
I was thinking in the long term of getting a FPGA development board, and I recall a board was being developed with a STM32 paired with a FPGA, but I cant remember the details.
But perhaps either of these FPGA analysers can double up as a general purpose FPGA dev board.
I will need to do some more research



